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uxn_opcodes.h
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uxn_opcodes.h
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#pragma once
#include "uintN_t.h" // uintN_t types for any N
#include <stdint.h>
#pragma once
#include "intN_t.h" // intN_t types for any N
#pragma once
#include "uxn_stack.h"
#pragma once
#include "uxn_device.h"
#pragma once
#include "uxn_constants.h"
/* Registers
[ Z ][ Y ][ X ][ L ][ N ][ T ] <
[ . ][ . ][ . ][ H2 ][ . ] <
[ L2 ][ N2 ][ T2 ] <
*/
typedef struct opcode_result_t {
uint1_t is_pc_updated;
uint1_t is_stack_index_flipped;
int4_t sp_relative_shift; // updated stack pointer value
uint1_t is_stack_write;
uint4_t stack_address_sp_offset;
uint1_t is_ram_write;
uint1_t is_device_ram_write;
uint8_t device_ram_address;
uint1_t is_vram_write;
uint1_t vram_write_layer;
uint8_t u8_value; // for stack_value, ram_value, vram_value, device_ram_value
uint16_t u16_value; // for pc value, vram address write, or ram address read
uint1_t is_opc_done;
} opcode_result_t;
typedef struct eval_opcode_result_t {
uint1_t is_waiting;
uint1_t is_pc_updated;
uint1_t is_ram_write;
uint1_t is_vram_write;
uint1_t vram_write_layer;
uint1_t is_device_ram_write;
uint8_t device_ram_address;
uint8_t u8_value; // for ram_value, vram_value, device_ram_value
uint16_t u16_value; // for pc value, vram address write, or ram address read
uint1_t is_opc_done;
} eval_opcode_result_t;
uint16_t u16_add_u8_as_i8(uint16_t u16, uint8_t u8) {
uint1_t is_negative = u8(7);
return is_negative ? (u16 - 0x0080 + (uint16_t)(u8 & 0x7F)) : (u16 + u8);
}
int4_t sp_relative_shift(uint8_t ins, int4_t x, int4_t y) {
return (((ins & 0x80) != 0) ? x + y : y);
}
opcode_result_t jci(uint8_t phase, uint16_t pc, uint8_t previous_stack_read, uint8_t previous_ram_read) {
// t=T; SHIFT(-1) if(!t) { pc += 2; break; } else { rr = ram + pc; pc += PEEK2(rr) + 2; }
static uint16_t tmp16;
static uint8_t t8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JCI ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.u16_value = pc; // peek RAM (byte 1 of 2) at address equal to PC
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1;
result.sp_relative_shift = -1;
result.u16_value = pc + 1; // peek RAM (byte 2 of 2) at address equal to PC + 1
}
else if (phase == 2) {
t8 = previous_stack_read;
tmp16 = (uint16_t)(previous_ram_read);
tmp16 <<= 8;
result.sp_relative_shift = 0;
}
else if (phase == 3) {
tmp16 |= ((uint16_t)(previous_ram_read));
result.is_pc_updated = 1;
result.u16_value = t8 == 0 ? pc + 2 : (pc + tmp16 + 2);
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jmi(uint8_t phase, uint16_t pc, uint8_t previous_ram_read) {
// rr = ram + pc; pc += PEEK2(rr) + 2;
static uint16_t tmp16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JMI ***\n************\n");
#endif
result.is_stack_write = 0;
result.is_stack_index_flipped = 0;
result.sp_relative_shift = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.u16_value = pc; // peek RAM (byte 1 of 2) at address equal to PC
result.is_opc_done = 0;
}
else if (phase == 1) {
result.u16_value = pc + 1; // peek RAM (byte 2 of 2) at address equal to PC + 1
}
else if (phase == 2) {
tmp16 = (uint16_t)(previous_ram_read);
tmp16 <<= 8;
}
else if (phase == 3) {
tmp16 |= (uint16_t)(previous_ram_read);
result.is_pc_updated = 1;
result.u16_value = (pc + tmp16 + 2);
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jsi(uint8_t phase, uint16_t pc, uint8_t previous_ram_read) {
// SHIFT( 2) T2_(pc + 2); rr = ram + pc; pc += PEEK2(rr) + 2;
static uint16_t tmp16 = 0;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JSI ***\n************\n");
#endif
tmp16 = pc + 2;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.sp_relative_shift = 2; // shift(2)
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = tmp16(7, 0); // set T2 (low byte)
result.u16_value = pc; // peek RAM (byte 1 of 2) at address equal to PC
result.is_opc_done = 0;
}
else if (phase == 1) {
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 2;
result.u8_value = tmp16(15, 8); // set T2 (high byte)
result.u16_value = pc + 1; // peek RAM (byte 2 of 2) at address equal to PC + 1
}
else if (phase == 2) {
tmp16 = (uint16_t)(previous_ram_read);
tmp16 <<= 8;
result.is_stack_write = 0;
}
else if (phase == 3) {
tmp16 |= ((uint16_t)(previous_ram_read));
result.is_pc_updated = 1;
result.u16_value = pc + tmp16 + 2; // pc += PEEK2_RAM(pc) + 2
result.is_opc_done = 1;
}
return result;
}
opcode_result_t lit(uint8_t phase, uint16_t pc, uint8_t previous_ram_read) {
// SHIFT( 1) T = ram[pc++];
#if DEBUG
printf("************\n**** LIT ***\n************\n");
#endif
opcode_result_t result;
result.is_stack_index_flipped = 0;
result.is_pc_updated = phase == 1 ? 1 : 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.sp_relative_shift = phase == 0 ? 1 : 0; // shift(1)
result.stack_address_sp_offset = 1;
result.is_stack_write = phase == 2 ? 1 : 0;
result.u8_value = phase == 2 ? previous_ram_read : 0;
result.u16_value = phase == 2 ? 0 : pc + phase; // peek RAM at at address equal to PC
result.is_opc_done = phase == 2 ? 1 : 0;
return result;
}
opcode_result_t lit2(uint8_t phase, uint16_t pc, uint8_t previous_ram_read) {
// SHIFT( 2) rr = ram + pc; T2_(PEEK2(rr)) pc += 2;
static uint4_t offsets[4] = {0, 0, 2, 1};
static uint1_t stack_writes[4] = {0, 0, 1, 1};
#if DEBUG
printf("************\n**** LIT2 ***\n************\n");
#endif
opcode_result_t result;
result.is_stack_index_flipped = 0;
result.is_pc_updated = phase == 2 ? 1 : 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.sp_relative_shift = phase == 0 ? 2 : 0;
result.stack_address_sp_offset = offsets[phase];
result.is_stack_write = stack_writes[phase];
result.u8_value = previous_ram_read;
result.u16_value = phase == 3 ? 0 : pc + phase;
result.is_opc_done = phase == 3 ? 1 : 0;
return result;
}
opcode_result_t pop(uint8_t ins) {
// SET(1,-1)
#if DEBUG
printf("************\n**** POP ***\n************\n");
#endif
opcode_result_t result;
result.is_stack_write = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.sp_relative_shift = sp_relative_shift(ins, 1, -1);
result.is_opc_done = 1;
return result;
}
opcode_result_t pop2(uint8_t ins) {
// SET(2,-2)
#if DEBUG
printf("************\n**** POP2 ***\n************\n");
#endif
opcode_result_t result;
result.is_stack_write = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.sp_relative_shift = sp_relative_shift(ins, 2, -2);
result.is_opc_done = 1;
return result;
}
opcode_result_t ovr(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T;n=N; SET(2, 1) T = n; N = t; L = n;
static uint8_t t8, n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** OVR ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, 1);
result.is_stack_write = 1;
result.stack_address_sp_offset = 2;
result.u8_value = t8; // set N
}
else if (phase == 3) {
n8 = previous_stack_read;
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 1;
result.u8_value = n8; // set T
}
else if (phase == 4) {
result.stack_address_sp_offset = 3;
result.u8_value = n8; // set L
result.is_opc_done = 1;
}
return result;
}
opcode_result_t ovr2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2;n=N2; SET(4, 2) T2_(n) N2_(t) L2_(n) break;
static uint8_t t16_low, t16_high, n16_low, n16_high;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** OVR2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16_high = previous_stack_read;
result.stack_address_sp_offset = 4; // get N2 (byte 1 of 2)
}
else if (phase == 3) {
t16_low = previous_stack_read;
result.stack_address_sp_offset = 3; // get N2 (byte 2 of 2)
}
else if (phase == 4) {
n16_high = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 4, 2);
result.is_stack_write = 1;
result.stack_address_sp_offset = 3;
result.u8_value = t16_low; // set N2 = previous T2 (low byte)
}
else if (phase == 5) {
n16_low = previous_stack_read;
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 4;
result.u8_value = t16_high; // set N2 = previous T2 (high byte)
}
else if (phase == 6) {
result.stack_address_sp_offset = 1;
result.u8_value = n16_low; // set T2 = previous N2 (low byte)
}
else if (phase == 7) {
result.stack_address_sp_offset = 2;
result.u8_value = n16_high; // set T2 = previous N2 (high byte)
}
else if (phase == 8) {
result.stack_address_sp_offset = 5;
result.u8_value = n16_low; // set L2 = previous N2 (low byte)
}
else if (phase == 9) {
result.stack_address_sp_offset = 6;
result.u8_value = n16_high; // set L2 = previous N2 (high byte)
result.is_opc_done = 1;
}
return result;
}
opcode_result_t dei(uint8_t phase, uint8_t ins, uint8_t controller0_buttons, uint32_t time, uint8_t stack_ptr0, uint8_t stack_ptr1, uint8_t previous_stack_read, uint8_t previous_device_ram_read) {
// t=T; SET(1, 0) T = DEI(t);
static uint1_t has_written_to_t;
static uint8_t t8;
static device_in_result_t device_in_result;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** DEI ***\n************\n");
#endif
has_written_to_t = 0;
result.sp_relative_shift = 0;
result.is_stack_write = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
result.is_device_ram_write = 0;
device_in_result.is_dei_done = 0;
}
else if (phase == 1) {
result.sp_relative_shift = sp_relative_shift(ins, 1, 0);
}
else {
result.sp_relative_shift = 0;
t8 = (phase == 2) ? previous_stack_read : t8;
if (~device_in_result.is_dei_done) {
device_in_result = device_in(t8, phase - 2, controller0_buttons, time, stack_ptr0, stack_ptr1, previous_device_ram_read);
result.device_ram_address = device_in_result.device_ram_address;
} else {
if (~has_written_to_t) {
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = device_in_result.dei_value;
has_written_to_t = 1;
} else {
result.is_stack_write = 0;
result.is_opc_done = 1;
}
}
}
return result;
}
opcode_result_t dei2(uint8_t phase, uint8_t ins, uint8_t controller0_buttons, uint32_t time, uint8_t stack_ptr0, uint8_t stack_ptr1, uint8_t previous_stack_read, uint8_t previous_device_ram_read) {
// t=T; SET(1, 1) T = DEI(t + 1); N = DEI(t);
static uint8_t t8, current_dei_phase, dei_param;
static uint1_t is_first_dei_done;
static device_in_result_t device_in_result;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** DEI2 ***\n************\n");
#endif
is_first_dei_done = 0;
current_dei_phase = 0;
result.sp_relative_shift = 0;
result.is_stack_write = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_device_ram_write = 0;
result.is_opc_done = 0;
device_in_result.is_dei_done = 0;
}
else if (phase == 1) {
result.sp_relative_shift = sp_relative_shift(ins, 1, 1);
}
else {
result.sp_relative_shift = 0;
t8 = (phase == 2) ? previous_stack_read : t8;
dei_param = is_first_dei_done ? t8 : t8 + 1;
device_in_result = device_in(dei_param, current_dei_phase, controller0_buttons, time, stack_ptr0, stack_ptr1, previous_device_ram_read);
if (device_in_result.is_dei_done) {
current_dei_phase = 0;
result.is_stack_write = 1;
result.is_opc_done = is_first_dei_done;
result.stack_address_sp_offset = is_first_dei_done ? 2 : 1; // set T and then N
result.u8_value = device_in_result.dei_value;
is_first_dei_done = 1;
} else {
result.device_ram_address = device_in_result.device_ram_address;
result.is_stack_write = 0;
current_dei_phase += 1;
}
}
return result;
}
opcode_result_t deo(uint12_t phase, uint8_t ins, uint8_t previous_stack_read, uint8_t previous_device_ram_read, uint8_t previous_ram_read) {
// t=T;n=N; SET(2,-2) DEO(t, n)
static uint8_t t8, n8;
static opcode_result_t result;
static device_out_result_t device_out_result;
if (phase == 0) {
#if DEBUG
printf("************\n**** DEO ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, -2);
}
else {
result.sp_relative_shift = 0;
n8 = (phase == 3) ? previous_stack_read : n8;
device_out_result = device_out(t8, n8, phase - 3, previous_device_ram_read, previous_ram_read);
result.is_device_ram_write = device_out_result.is_device_ram_write;
result.device_ram_address = device_out_result.device_ram_address;
result.u8_value = device_out_result.u8_value;
result.u16_value = device_out_result.u16_addr;
result.is_vram_write = device_out_result.is_vram_write;
result.vram_write_layer = device_out_result.vram_write_layer;
result.is_opc_done = device_out_result.is_deo_done;
}
return result;
}
opcode_result_t deo2(uint12_t phase, uint8_t ins, uint8_t previous_stack_read, uint8_t previous_device_ram_read, uint8_t previous_ram_read) {
// t=T;n=N;l=L; SET(3,-3) DEO(t, l) DEO((t + 1), n)
static uint8_t t8, n8, l8, deo_param0, deo_param1;
static uint12_t current_deo_phase;
static uint1_t is_second_deo = 0, is_phase_3 = 0, is_phase_4 = 0;
static opcode_result_t result;
static device_out_result_t device_out_result;
if (phase == 0) {
#if DEBUG
printf("************\n*** DEO2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
is_second_deo = 0;
current_deo_phase = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 3; // get L
}
else if (phase == 2) {
result.stack_address_sp_offset = 2; // get N
t8 = previous_stack_read;
}
else {
is_phase_3 = (phase == 3) ? 1 : 0;
is_phase_4 = (phase == 4) ? 1 : 0;
l8 = is_phase_3 ? previous_stack_read : l8;
n8 = is_phase_4 ? previous_stack_read : n8;
deo_param0 = is_second_deo ? t8 + 1 : t8;
deo_param1 = is_second_deo ? n8 : l8;
result.sp_relative_shift = is_phase_3 ? sp_relative_shift(ins, 3, -3) : 0;
device_out_result = device_out(deo_param0, deo_param1, current_deo_phase, previous_device_ram_read, previous_ram_read);
result.is_device_ram_write = device_out_result.is_device_ram_write;
result.device_ram_address = device_out_result.device_ram_address;
result.is_vram_write = device_out_result.is_vram_write;
result.vram_write_layer = device_out_result.vram_write_layer;
result.u16_value = device_out_result.u16_addr;
result.u8_value = device_out_result.u8_value;
result.is_opc_done = device_out_result.is_deo_done & is_second_deo;
if (device_out_result.is_deo_done) {
current_deo_phase = 0;
is_second_deo = 1;
} else {
current_deo_phase += 1;
}
}
return result;
}
opcode_result_t jmp(uint8_t phase, uint8_t ins, uint16_t pc, uint8_t previous_stack_read) {
// t=T; SET(1,-1) pc += (Sint8)t;
static uint8_t t8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JMP ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1;
}
else if (phase == 2) {
t8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 1, -1);
result.is_pc_updated = 1;
result.u16_value = u16_add_u8_as_i8(pc, t8);
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jmp2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2; SET(2,-2) pc = t
static uint16_t t16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** JMP2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16 = (uint16_t)(previous_stack_read);
t16 <<= 8;
}
else if (phase == 3) {
t16 |= ((uint16_t)(previous_stack_read));
result.sp_relative_shift = sp_relative_shift(ins, 2, -2);
result.is_pc_updated = 1;
result.u16_value = t16; // pc = t16
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jcn(uint8_t phase, uint8_t ins, uint16_t pc, uint8_t previous_stack_read) {
// t=T;n=N; SET(2,-2) if(n) pc += (Sint8)t;
static uint8_t t8, n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JCN ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
}
else if (phase == 3) {
n8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, -2);
result.is_pc_updated = 1;
result.u16_value = n8 == 0 ? pc : u16_add_u8_as_i8(pc, t8); // if(n) pc += (Sint8)t;
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jcn2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2;n=L; SET(3,-3) if(n) pc = t;
static uint16_t t16;
static uint8_t n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** JCN2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16 = (uint16_t)(previous_stack_read);
t16 <<= 8;
result.stack_address_sp_offset = 3; // get L
}
else if (phase == 3) {
t16 |= ((uint16_t)(previous_stack_read));
}
else if (phase == 4) {
n8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 3, -3);
result.is_pc_updated = n8 == 0 ? 0 : 1;
result.u16_value = n8 == 0 ? 0 : t16; // if(n) pc = t;
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jsr(uint8_t phase, uint8_t ins, uint16_t pc, uint8_t previous_stack_read) {
// t=T; SET(1,-1) FLIP SHIFT(2) T2_(pc) pc += (Sint8)t;
static uint8_t t8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** JSR ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1;
result.sp_relative_shift = sp_relative_shift(ins, 1, -1);
}
else if (phase == 2) {
t8 = previous_stack_read;
result.is_stack_index_flipped = 1;
result.sp_relative_shift = 2;
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = pc(7, 0); // set T2 (low byte)
}
else if (phase == 3) {
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 2;
result.u8_value = pc(15, 8); // set T2 (high byte)
result.is_pc_updated = 1;
result.u16_value = u16_add_u8_as_i8(pc, t8); // pc += t
result.is_opc_done = 1;
}
return result;
}
opcode_result_t jsr2(uint8_t phase, uint8_t ins, uint16_t pc, uint8_t previous_stack_read) {
// t=T2; SET(2,-2) FLIP SHIFT(2) T2_(pc) pc = t;
static uint16_t t16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** JSR2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16 = (uint16_t)(previous_stack_read);
t16 <<= 8;
result.sp_relative_shift = sp_relative_shift(ins, 2, -2);
}
else if (phase == 3) {
t16 |= ((uint16_t)(previous_stack_read));
result.is_stack_index_flipped = 1;
result.sp_relative_shift = 2;
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = pc(7, 0); // set T2 (low byte)
}
else if (phase == 4) {
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 2;
result.u8_value = pc(15, 8); // set T2 (high byte)
result.is_pc_updated = 1;
result.u16_value = t16; // pc = t16
result.is_opc_done = 1;
}
return result;
}
opcode_result_t add(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T;n=N; SET(2,-1) T = n + t;
static uint8_t t8, n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** ADD ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
}
else if (phase == 3) {
n8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, -1);
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = n8 + t8; // set T
result.is_opc_done = 1;
}
return result;
}
opcode_result_t add2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2;n=N2; SET(4,-2) T2_(n + t)
static uint16_t t16, n16, tmp16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** ADD2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16 = (uint16_t)(previous_stack_read);
t16 <<= 8;
result.stack_address_sp_offset = 4; // get N2 (byte 1 of 2)
}
else if (phase == 3) {
t16 |= ((uint16_t)(previous_stack_read));
result.stack_address_sp_offset = 3; // get N2 (byte 2 of 2)
}
else if (phase == 4) {
n16 = (uint16_t)(previous_stack_read);
n16 <<= 8;
}
else if (phase == 5) {
n16 |= ((uint16_t)(previous_stack_read));
tmp16 = t16 + n16;
result.sp_relative_shift = sp_relative_shift(ins, 4, -2);
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = (uint8_t)(tmp16); // set T2 (low byte)
}
else if (phase == 6) {
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 2;
result.u8_value = (uint8_t)(tmp16 >> 8); // set T2 (high byte)
result.is_opc_done = 1;
}
return result;
}
opcode_result_t and(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T;n=N; SET(2,-1) T = n & t;
static uint8_t t8, n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** AND ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
}
else if (phase == 3) {
n8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, -1);
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = n8 & t8; // set T
result.is_opc_done = 1;
}
return result;
}
opcode_result_t and2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2;n=N2; SET(4,-2) T2_(n & t)
static uint16_t t16, n16, tmp16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** AND2 ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 2; // get T2 (byte 1 of 2)
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 1; // get T2 (byte 2 of 2)
}
else if (phase == 2) {
t16 = (uint16_t)(previous_stack_read);
t16 <<= 8;
result.stack_address_sp_offset = 4; // get N2 (byte 1 of 2)
}
else if (phase == 3) {
t16 |= ((uint16_t)(previous_stack_read));
result.stack_address_sp_offset = 3; // get N2 (byte 2 of 2)
}
else if (phase == 4) {
n16 = (uint16_t)(previous_stack_read);
n16 <<= 8;
}
else if (phase == 5) {
n16 |= ((uint16_t)(previous_stack_read));
tmp16 = t16 & n16;
result.sp_relative_shift = sp_relative_shift(ins, 4, -2);
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = (uint8_t)(tmp16); // set T2 (low byte)
}
else if (phase == 6) {
result.sp_relative_shift = 0;
result.stack_address_sp_offset = 2;
result.u8_value = (uint8_t)(tmp16 >> 8); // set T2 (high byte)
result.is_opc_done = 1;
}
return result;
}
opcode_result_t ora(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T;n=N; SET(2,-1) T = n | t;
static uint8_t t8, n8;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n**** ORA ***\n************\n");
#endif
result.is_stack_write = 0;
result.sp_relative_shift = 0;
result.is_stack_index_flipped = 0;
result.is_pc_updated = 0;
result.is_ram_write = 0;
result.is_vram_write = 0;
result.stack_address_sp_offset = 1; // get T
result.is_opc_done = 0;
}
else if (phase == 1) {
result.stack_address_sp_offset = 2; // get N
}
else if (phase == 2) {
t8 = previous_stack_read;
}
else if (phase == 3) {
n8 = previous_stack_read;
result.sp_relative_shift = sp_relative_shift(ins, 2, -1);
result.is_stack_write = 1;
result.stack_address_sp_offset = 1;
result.u8_value = n8 | t8; // set T
result.is_opc_done = 1;
}
return result;
}
opcode_result_t ora2(uint8_t phase, uint8_t ins, uint8_t previous_stack_read) {
// t=T2;n=N2; SET(4,-2) T2_(n | t)
static uint16_t t16, n16, tmp16;
static opcode_result_t result;
if (phase == 0) {
#if DEBUG
printf("************\n*** ORA2 ***\n************\n");
#endif
result.is_stack_write = 0;